In recent years, for the purpose of narrowing edges of a liquid crystal display device, there have been demands for a reduction in size of a display drive circuit that drives a liquid crystal panel. Since a size of a display drive circuit is largely affected by the number of transistors by which the display drive circuit is configured, it is important to reduce the number of transistors.
An example of a conventional display drive circuit is a shift register for use in a scan signal line drive circuit (gate driver) (e.g. Patent Literature 1). FIG. 33 is a block diagram schematically illustrating a configuration of a conventional shift register. FIG. 34 is a circuit diagram illustrating one of stages (hereinafter referred to as “SR unit circuit(s)”) by which the shift register is configured.
As illustrated FIG. 34, the SR unit circuit includes an RS flip-flop 110 and a clock outputting section 120. The RS flip-flop (hereinafter referred to as “flip-flop”) 110 includes (i) a P-channel transistor P100 and an N-channel transistor N101 by which a CMOS circuit is configured, (ii) a P-channel transistor P101 and an N-channel transistor N102 by which a CMOS circuit is configured, (iii) an N-channel transistor N100, (iv) an S terminal (set terminal), (v) an R terminal (reset terminal), (vi) an INITB terminal (initial terminal), (vii) a Q terminal, and (viii) a QB terminal. A gate terminal of the transistor P100, a gate terminal of the transistor N101, a drain terminal of the transistor N100, a drain terminal of the transistor P101, a drain terminal of the transistor N102, and the Q terminal are connected to one another. A drain terminal of the transistor P100, a drain terminal of the transistor N101, a gate terminal of the transistor P101, a gate terminal of the transistor N102, and the QB terminal are connected to one another. The R terminal is connected to a gate terminal of the transistor N100. The S terminal is connected to a source terminal of the transistor N100 and to a source terminal of the transistor N102. The INITB terminal is connected to a source terminal of the transistor P101. A source terminal of the transistor P100 is connected to a VDD. A source terminal of the transistor N101 is connected to a VSS.
The clock outputting section 120 includes (i) a P-channel transistor P102, (ii) N-channel transistors N103 and N104, (iii) a CKa terminal (clock terminal), and (iv) an O terminal (output terminal). A gate terminal of the transistor N104 and the Q terminal are connected to each other. A gate terminal of the transistor N103, a gate terminal of the transistor P102, and the QB terminal are connected to one another. A drain terminal of the transistor N103, a drain terminal of the transistor N104, a drain terminal of the transistor P102, and the O terminal are connected to one another. A source terminal of the transistor N104, a source terminal of the transistor P102, and the CKa terminal are connected to one another. A source terminal of the transistor N103 is connected to the VSS.
FIG. 35 is a timing chart illustrating an operation of the shift register illustrated in FIG. 33. The following description will discuss the operation of the shift register.
(Initialization Operation)
First, an operation in a case where initialization is carried out in response to an initializing signal INITB becoming active (having a low electric potential) will be described.
In a case where the electric potential of an INITB signal becomes low while the SR unit circuit is active (electric potentials at nodes Q and QB being high and low, respectively), the node Q (Q terminal) becomes connected to the INITB terminal, so that the electric potential at the node Q changes from a high level to a low level. This is because the transistor P101 is turned on. In a case where the electric potential at the node Q starts decreasing to the low level, the transistor N101 becomes turned off. This causes the transistor P100 to start becoming turned on, and therefore causes the electric potential at the node QB (QB terminal) to change from a low level to a high level.
In a case where the electric potentials at the Q terminal and at the QB terminal ultimately become low and high, respectively, the transistors N104 and P102 become turned off, and therefore the O terminal and the CKa terminal become disconnected from each other. In so doing, the transistor N103 becomes turned on, and therefore the O terminal outputs a signal having a low electric potential. Thereafter, the SR unit circuit remains inactive (the electric potentials at the nodes Q and QB being low and high, respectively) even in a case where the initializing signal INITB becomes inactive (having a high electric potential).
In a case where SR unit circuit is inactive immediately before the electric potential of the initializing signal INITB becomes low, the transistor P101 is turned off. This prevents the node Q from receiving the initializing signal INITB. However, since the SR unit circuit is already inactive, the O terminal is outputting a signal having a low electric potential. This causes the SR unit circuit to remain inactive even in a case where the electric potential of the initializing signal INITB becomes high.
The initializing signal INITB is supplied to each stage (the SR unit circuits of all stages) of the shift register. Therefore, in a case where the initializing signal INITB becomes active (having a low electric potential), the shift register is thus initialized. This allows the electric potentials of output signals from all the stages to be low.
(Operation of Flip-Flop)
Next, an operation of a flip-flop 110 will be described with reference to FIG. 34. Note that the electric potential of the initializing signal INITB is assumed to high.
The flip-flop in an inactive state has a high electric potential at the node QB (QB terminal). Hence, in a case where an active signal (having a high electric potential) is supplied to the S terminal (set terminal), the transistor N102 becomes turned on, and therefore the S terminal and the node Q (Q terminal) become connected to each other. This causes the electric potential at the node Q to change from a low level to a high level. In a case where the electric potential at the node Q changes to the high level, (i) the transistor N101 changes to an on state and (ii) the transistor P100 changes to an off state. This causes the electric potential at the node QB to change from a high level to a low level. Therefore, in a case where the S terminal becomes active, the flip-flop 110 becomes active (the electric potentials at the nodes Q and QB being high and low, respectively) as well.
In a case where an active signal (having a high electric potential) is supplied to the R terminal (reset terminal), the transistor N100 becomes turned on. This causes the S terminal and the node Q to be connected to each other. In so doing, an inactive signal (having a low electric potential) is supplied to the S terminal. This causes the electric potential at the node Q to change from the high level to the low level. In a case where the electric potential at the node Q changes to the low level, (i) the transistor P100 changes to an on state and (ii) the transistor N101 changes to an off state. This causes the electric potential at the node QB to change from the low level to the high level. Therefore, in a case where the R terminal becomes active, the flip-flop 110 becomes inactive (the electric potentials at the nodes Q and QB being low and high, respectively).
In a case where the S terminal and the R terminal both become inactive (having low electric potentials), (i) the transistor N100 is turned off and (ii) an inverter, which is made up of the transistors P100 and N101, and an inverter, which is made up of the transistors P101 and N102, are in a latched state. This causes a previous state to be maintained. Specifically, in a case where the S terminal and the R terminal both become inactive after the S terminal becomes active, the active state of the flip-flop 110 is maintained. On the other hand, in a case where the S terminal and the R terminal both become inactive after the R terminal becomes active, the inactive state of the flip-flop 110 is maintained.
(Operation of Clock Outputting Section)
The clock outputting section 120 receives output signals (Q, QB) from the flip-flop 110. In a case where the flip-flop 110 is active, (i) transistor N103 becomes turned off and (ii) the transistors P102 and N104 become turned on. This causes the O terminal and the CKa terminal of the SR unit circuit to be connected to each other, and therefore causes an output signal (O signal) to be outputted in accordance with an electric potential at the CKa terminal.
In a case where the flip-flop 110 is inactive, (i) the transistor N103 becomes turned on and (ii) the transistors P102 and N104 become turned off. This causes an electric potential of the output signal (O signal) from the SR unit circuit to be low.
(Operation of Shift Register)
In a case where a start pulse ST is supplied (set) to an S terminal of an SR unit circuit (SR100(1)) which is a first stage of the shift register illustrated in FIG. 33, a flip-flop 110 of the SR1 becomes active (an electric potential at Q1 being high). This causes a clock signal CK1, which is supplied to a CKa terminal of a clock outputting section 120, to be supplied to an O1 terminal. In a case where an electric potential of the clock signal CK1 changes from a low level to a high level, an active signal (having a high electric potential) is supplied to an S terminal of a second-stage SR unit circuit (SR100(2)), to which S terminal an output signal O1 is to be supplied. This causes a flip-flop 110 of the SR100(2) to become active (an electric potential at Q2 being high), and therefore causes a clock signal CK2, which is supplied to a CKa terminal of a clock outputting section 120, to be supplied to an O2 terminal. The O2 terminal is connected to an R terminal of the SR100(1) and to an S terminal of an SR100(3).
In a case where an electric potential of the clock signal CK2 becomes high after (i) the electric potential of clock signal CK1 changes from the high level to the low level and (ii) the electric potential of the output signal O1 becomes low, an electric potential of an output signal O2 becomes high. This causes a signal having a high electric potential to be supplied to the R terminal of the SR100(1). Therefore, (I) the flip-flop 110 of the SR100(1) becomes inactive (reset) and (II) a low electric potential of the output signal O1 is maintained. In addition, a signal having a high electric potential is supplied from the O2 terminal to the S terminal of the SR100(3). This causes a flip-flop of the SR100(3) to become active.
In a case where the electric potential of the clock signal CK2 changes from a high level to a low level, (i) the electric potential of the output signal O2 becomes low and (ii) the electric potentials of the S terminal and the R terminal of the SR100(1) become low. This causes the inactive state of the flip-flop 110 of the SR100(1) to be maintained. In a case where the present embodiment of the clock signal CK1 changes from a low level to a high level, a signal having a high electric potential is outputted from an O3 terminal of the SR100(3) and is then supplied to an R terminal of the SR100(2) which R terminal is connected to the O3 terminal. This causes the flip-flop of the SR100(2) to be inactive. In a case where (a) the present embodiment of the clock signal CK1 changes from a high level to a low level and (b) an electric potential of an output signal O3 becomes low, the electric potentials of the S terminal and the R terminal of the SR100(2) both become low. This causes the inactive state of the flip-flop 110 of the SR100(2) to be maintained.
The shift register thus causes a signal to be sequentially supplied to S terminals and R terminals of flip-flops 110 as well as causes a pulse to be sequentially outputted from O terminals.
Note that it is necessary to supply a signal to an R terminal of a last outputting stage SR100(n) of the shift register in order to cause a flip-flop 110 of the SR100(n) to be inactive after a pulse is outputted from an On terminal of the SR100(n). According to the conventional shift register, a dummy-stage SR100(d), which has a configuration identical to those of the SR unit circuits of other stages, is connected as a circuit for resetting the last outputting-stage SR100(n) (see FIG. 33). An output signal Od from the dummy-stage SR100(d) is supplied to inverters of a plurality of stages which are designed for delaying a pulse. Output from the inverters is supplied to an R terminal of the dummy-stage SR100(d) and to the R terminal of the last outputting-stage SR100(n).
In a case where an electric potential of an output signal On from the SR100(n) becomes high, the output signal On is supplied to an S terminal of the SR100(d). This causes a flip-flop 110 of the SR100(d) to be active. In a case where the electric potential of the clock signal CK1 supplied to the dummy-stage SR100(d) becomes high after (i) the electric potential of the clock signal CK2 becomes low and (ii) a pulse of the output signal On is outputted, a signal having a high electric potential is outputted from an Od terminal. A pulse of the output signal Od is delayed by the inverters, and is then supplied to the R terminal of the SR100(n) and to the R terminal of the SR100(d). This causes the flip-flops 110 of the SR100(n) and of the SR100(d) to become inactive (reset), and therefore causes the electric potential of the output signal Od to be low.
Since the flip-flop 110 of the last outputting-stage SR100(n) is thus made inactive and a resetting signal is thus supplied to the dummy-stage SR100(d), the flip-flop 110 of the dummy-stage can also be made inactive. Note that the reason for delaying the pulse of the output signal Od is to secure a time required for resetting the dummy-stage SR100(d).